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HM5216326 Series
262,144-word x 32-bit x 2-bank Synchronous Graphic RAM
ADE-203-678 (Z) Preliminary Rev. 0.0 Nov. 20, 1996 Description
All inputs and outputs signals refers to the rising edge of the clock input. The HM5216326 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for graphic applications.
Features
* * * * * * * 3.3V Power supply Clock frequency: 125 MHz/100 MHz/83 MHz (max) LVTTL interface 2 Banks can operates simultaneously and independently Burst read/write operation and burst read/ single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) Programmable CAS latency: 1/2/3 Byte control by DQM 8 column block write function with column address mask Write per bit function (old mask) Refresh cycles: 2048 refresh cycle/32 ms 2 variations of refresh Auto refresh Self refresh
* * * * * *
Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice.
HM5216326 Series
Ordering Information
Type No. HM5216326FP-8 HM5216326FP-10 HM5216326FP-12 Frequency 125 MHz 100 MHz 83 MHz Package 100-pin plastic LQFP (FP-100H)
Pin Arrangement
HM5216326FP Series
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC DQM3 DQM1 CLK CKE DSF NC A9 DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC VDD DQ0 DQ1 VSSQ DQ2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
A7 A6 A5 A4 VSS NC NC NC NC NC NC NC NC NC NC VDD A3 A2 A1 A0
2
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS A10 A8
(Top view)
HM5216326 Series
Pin Description
Pin name A0 to A10 Function Address input Row address Column address Bank select address (BS) DQ0 to DQ31 CS RAS CAS WE DQM0 to DQM3 CLK CKE VDD VSS VDDQ VSS Q DSF NC Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ internal circuit Ground for DQ internal circuit Special function input flag No connection A0 to A9 A0 to A7 A10
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HM5216326 Series
Block Diagram
A0 to A10
A0 to A7
A0 to A10
Column address counter
Column address buffer
Row address buffer
Refresh counter
Row decoder
Row decoder
Sense amplifier & I/O bus
Column decoder
Bank 0
1024 row x 256 column x 32 bit
Column decoder
Memory array
Sense amplifier & I/O bus
Memory array
Bank 1
1024 row x 256 column x 32 bit
DQ0 to DQ31
DQM3 DQM2 DQM1 DQM0 CKE RAS CAS CLK DSF WE CS
4
Color register
Mask register
Input buffer
Output buffer
Control logic & timing generator
HM5216326 Series
Pin Functions
CLK (input pin): CLK is the master clock input pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. DSF (input pin): DSF is a part of inputs of graphic commands of the HM5216326. If DSF is LOW, the HM5216326 operates as standard synchronous DRAM. A0 to A9 (input pins): Row address (AX0 to AX9) is determined by A0 to A9 pins at the CLK rising edge when a bank active command is input. Column address (AY0 to AY7) is determined by levels on A0 to A7 pins at the CLK rising edge when a read or write command is input. A9 determins precharge mode. When A9 is low, only the bank selected by A10 (BS) is precharged by a precharge command. When A9 is high, both banks are precharged by a precharge command. A10 (input pin): A10 is the bank select signal (BS). The memory array of the HM5216326 is divided into the bank 0 and the bank 1, both contain 1024 row x 256 column x 32 bits. If A10 is Low, the bank 0 is selected, and if A10 is High, the bank 1 is selected. CKE (input pin): By referring low level on CKE pin, HM5216326 determines to go into clock suspend modes or power down modes. When refresh command is input, low level on this pin is also referred to turn on self refresh process. DQM0, DQM1, DQM2 and DQM3 (input pins): DQM0 applies to DQ0 to DQ7. DQM1 applies to DQ8 to DQ15. DQM2 applies to DQ16 to DQ23. DQM3 applies to DQ24 to DQ31. In read mode, referring high level on DQM pins, HM5216326 floats related DQ pins. In write mode, referring high level on DQM pins, HM5216326 ignores input data through related DQ pins. DQ0 to DQ31 (input/output): These are the data line for the HM5216326. VDD and VDDQ (power supply pins): 3.3 V is applied. (VDD is for the internal circuit and VDDQ is power supply pin for DQ output buffer.) VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSS Q is for DQ output buffer.)
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HM5216326 Series
Simplified State Diagram
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
SMRS ACTIVM
SPECIAL MODE REGISTER SET
CKE CKE_ ACTIV IDLE POWER DOWN
CKE_ SMRS
BST
Active Suspend
ROW ACTIVE
CKE
BST
WRITE Write CKE_ WRITE/ BWRITE SUSPEND CKE WRITE/ BWRITE WRITE/ BWRITE WITH AP READ READ WITH AP
READ Read CKE_ READ CKE READ WITH AP CKE_ READA CKE READA SUSPEND READ SUSPEND
WRITE WITH AP WRITE/ BWRITEA SUSPEND CKE_ CKE
WRITE/ BWRITE READ WRITE/ WITH AP BWRITE WITH AP PRECHARGE
WRITE/ BWRITEA PRECHARGE PRECHARGE
POWER APPLIED
POWER ON
PRECHARGE PRECHARGE
Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
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HM5216326 Series
Commands Operation
Commands Explanation Every operations of HM5216326 are executed by input commands. A command is input, at the rising edge of CLK, by setting the levels on CS, RAS, CAS, WE, A9 (precharge control) and DSF pins, HIGH (VIH) or LOW (VIL ). Note: The setup and hold condition should be obeyed when command, address or data is input. Setup and Hold Condition of Command, Address and Data Input
CLK
Command tCMS t CMH
Address t AS t AH
Data t DS t DH
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HM5216326 Series
Precharge command [PRE, PALL]: At the CLK rising edge, by setting CS, RAS, WE, DSF are LOW, CAS is HIGH bank can be precharged to idle state. A9 = LOW: A9 = HIGH: [State transition] power on -- (precharge) -> Idle Row active -- (precharge) -> Idle Precharge Command the bank selected by A10 is precharged. both banks are precharged.
CLK CKE CS RAS CAS WE DSF A9 VIH

A10 A0 to A8 DQ High-Z 8
HM5216326 Series
Mode register set command [MRS]: If both banks have been precharged or are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, WE, DSF; LOW an internal register (the mode register; MRS) are set. The data through address pins, at the cycle when this command is input, are stored in the mode register. A8, A9, A10 bits determine burst write or single write. A4 to A6 bits determine CAS latency. A3 bit determines burst type, sequential or interleave. A0 to A2 bits determine burst length. A7 bit should be set to low. See table below for details. [State transition] Idle -- (Mode resister set) ->Idle Mode Register Set Command
CLK CKE CS RAS CAS WE DSF A8 to A10 A6 to A4 A3 A2 to A0 A7 DQ High-Z OP CODE CAS Latency Burst type Burst length VIH
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HM5216326 Series
Mode Register Configuration
A10 0 x 0 x A9 0 0 1 1 A8 0 1 0 1 Operation CODE Burst read and burst write R Burst read and single write R
A6 0 0 0 0 1
A5 0 0 1 1 x
A4 0 1 0 1 x
CAS latency R 1 2 3 R
A3 0 1
Burst type Sequencial Interleave
Burst length A2 0 0 0 0 1 1 1 1 Note: R: Reserved A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 R R R Full page BT = 1 1 2 4 8 R R R R
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HM5216326 Series
Bank and row active command [ACTV, ACTVM]: If a bank has been precharged or is in idle state. At the CLK rising edge, by setting CS, RAS; LOW, CAS, WE: HIGH a row of the bank is activated. The bank is selected by setting the level on A10 pin HIGH (bank 1) or LOW (bank 0) at this timing. A0 to A9 determine the row address. [Option] DSF = LOW; DSF = HIGH; [State transition] Idle -- (row active) ->Row active Bank and Row Active Command write per bit function disable (ACTV) write per bit function enable (ACTVM)
CLK CKE CS RAS CAS WE DSF A10 A0 to A9 DQ High-Z VIH
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HM5216326 Series
Column address and read command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF; LOW, RAS, WE; HIGH, data is output through DQ pins. A10 determines the bank address. A0 to A7 determine the column address. CAS latency stored in MRS determines the timing when data are driven. In case, CL (CAS latency) = 1, 1 clock cycle after the command input, data start to be output. In case CL = 2, 2 clock cycle after the command input, data start to be output. In case CL = 3, 3 clock cycle after the command input, data start to be output. Burst Length (BL) stored in MRS determines data length of output . [Option] A9 = HIGH; A9 = LOW; [State transition] Row active -- (Column address and read command) ->Row active Row active -- (Column address and read command) ->Idle (auto precharge) auto precharge mode or execute precharge automatically after finishing data output. Read mode without auto precharge.
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HM5216326 Series
Column Address and Read Command (CL = 1, BL = 1)
CLK CKE CS RAS CAS WE DSF A9 A10 A0 to A7 DQ (out) High-Z VIH
Column address and write command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF, WE; LOW, RAS; HIGH, the data on DQ pins are input. A10 determines the bank address. A0 to A7 determine the column address. For write, data should start to be input at the same cycle of the command input. Burst length stored in MRS determines the expected data length to be input. If the bank, for which command is input, is activated by ACTVM, then I/O bit mask function or write per bit is available. [Option] A9 = HIGH; A9 = LOW; [State transition] auto precharge mode or execute precharge automatically after finishing data input. write mode without auto precharge.
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HM5216326 Series
Row active -- (Column address and write command) ->Row active Row active -- (Column address and write command) ->Idle (auto precharge case) Column Address and Write Command (BL = 2)
CLK CKE CS RAS CAS WE DSF A9 A10 A0 to A7 DQ (in) High-Z VIH
Burst stop command (BST): At the CLK rising edge, by setting CS, WE, DSF: LOW, RAS, CAS; HIGH, full page burst (BL = 256) read/write is interupted. If BL is set to 1, 2, 4, 8, to try to execute this command is illegal. [State transition] Row active -- (Burst stop command) -> Row active
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HM5216326 Series
Burst Stop Command
CLK CKE CS RAS CAS WE VIH

DSF A0 to A10 15
HM5216326 Series
Auto refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, DSF; LOW, WE; HIGH, the HM5216326 starts auto-refresh (CBR type) operation. Refresh address is internaly generated. No precharge commands are required after autorefresh, since precharge is automatically performed for both banks. [State transition] Idle -- (Auto refresh command) -> Idle Auto Refresh Command
CLK CKE CS RAS CAS WE VIH

DSF A0 to A10 DQ High-Z 16
HM5216326 Series
Self refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, DSF; LOW, WE; HIGH, and if CKE's falling edge is detected, the HM5216326 starts self-refresh operation. Self-refresh operation is kept while CKE is LOW. [State transition] Idle -- (Self refresh command) -> Self refresh mode Self Refresh Command
CLK CKE CS RAS CAS WE

DSF A0 to A10 DQ High-Z 17
HM5216326 Series
No operation command (NOP): At the CLK rising edge, by setting CS; LOW, WE, RAS, CAS; HIGH, [State transition] No transition No Operation Command
CLK CKE CS RAS CAS WE VIH

DSF A0 to A10 DQ High-Z
Ignore command (DESL): At the CLK rising edge, by setting CS; HIGH, any input is ignored.
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HM5216326 Series
Graphic Commands Special mode register set command (SMRS): If each banks is in idle state or activated, at the CLK rising edge, by setting CS, RAS, CAS, WE; LOW, DSF; HIGH, an internal register (the special mode register; SMRS) are set. The data through address pins, at the cycle when this command is input, are stored in the special mode register. A0 to A4: reserved. should be LOW when SMRS is issued. A5: determines whether loading mask data or not when SMRS is issued. A6: determines whether loading color data or not when SMRS is issued. A7 to A10: reserved. should be set LOW when SMRS is issued. In case A5 bit of the mode register = HIGH, the data through DQ pins, at the cycle this command is issued, are stored in the MASK register (32 bits). If write per bit function is available*, and DQi (i = 0,..,31)bit of the MASK register = LOW, DQi data path to memory array is masked. In case A6 bit of the mode register HIGH, the data through DQ pins, at the cycle when this command is issued, are stored in the COLOR register (32 bits). This specific data is written to 8 columns in one clock cycle by block write command. Note: When bank active command is issued and DSF set to LOW, write per bit function is enabled.
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HM5216326 Series
Special Mode Register Set Command
CLK CKE CS RAS CAS WE DSF A0 to A4 A5 A6 A7 to A10 Load mask Load color VIH
DQ
High-Z
Special Mode Register Configuration
A5 0 1 x 0 1 Note: x: VIH or VIL A6 x 0 0 1 1 Function Disable Enable Disable Enable ILLEGAL Load Color Load Mask
Reserved Bits
A0 0 A1 0 A2 0 A3 0 A4 0 A7 0 A8 0 A9 0 A10 0
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HM5216326 Series
Graphic Function Block Diagram
MASK register DQ 0 DQ 1 0 1
DQ 30 DQ 31
30 31
COLOR register 0 1
30 31
Memory Array
I1 I2
When block write command is issued, data I1 stored in the COLOR register is loaded O into column block (8 columns) of memory array. For burst and single write, the data I2 from DQ pins are loaded into a single column. When write per bit function is available, if mask data I1 stored in the MASK register is LOW then the data path from I2 to O is cut.
I1 I2 O
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HM5216326 Series
Column address and block write command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, WE; LOW, RAS, DSF; HIGH, a block write *2 is executed. A10 determines the bank address. A0 to A1 HIGH or LOW (ignored). A3 to A7 determine the column block address. The data through DQ pins, at the cycle when the block write command input, are referred to stop the color data to be written onto the specific column. (Column mask) [Option] A9 = HIGH; Auto precharge mode or execute precharge automatically after finishing a block write execution. A9 = LOW; Write mode without auto precharge. [State transition] Row active -- (Block write command) ->Row active Row active -- (Block write command) ->Idle(auto precharge case)
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HM5216326 Series
Column Address and Block Write Command
CLK CKE CS RAS CAS WE DSF A9 A10 A0 to A7 DQ High-Z VIH
Column Block
Column location A0 0 1 0 1 0 1 0 1 Note: A1 0 0 1 1 0 0 1 1 A2 0 0 0 0 1 1 1 1 Column block location A3 a3 a3 a3 a3 a3 a3 a3 a3 A4 a4 a4 a4 a4 a4 a4 a4 a4 A5 a5 a5 a5 a5 a5 a5 a5 a5 A6 a6 a6 a6 a6 a6 a6 a6 a6 A7 a7 a7 a7 a7 a7 a7 a7 a7
1. a3, a4, a5, a6, a7; VIH or VIL.
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HM5216326 Series
DQ Input at the Block Write Cycle and Column Mask Location
Column location DQ pin NO. DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ group* 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11
1
Column mask A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 No mask High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High Mask Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Note: DQ group: 00; DQ0 to DQ7, 01; DQ8 to DQ15, 10; DQ16 to DQ23, 11; DQ24 to DQ31
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HM5216326 Series
Command Truth Table The HM5216326 recognizes the following commands specified by the CS, RAS, CAS, WE, DSF and address pins. All other combinations than those in the table bellow are illegal.
Function Ignore command No operation Burst stop in full page Column address and read command Read with auto precharge Column address and write command Write with auto precharge Row address strobe and bank active Precharge select bank Precharge all bank Refresh (auto, self) Mode register set CKE Symbol n - 1 n DESL*2 H NOP BST*
3
CS RAS CAS WE DSF A10 A9 H L L L L L L L L L L L L L L L x H H H H H H L L L L L L H H L x H H L L L L H H H L L H L L L x H L H H L L H L L H L H L L L x x L L L L L L L L L L H H H H x x x V V V V V V x x V V V V L x x x L H L H V L H x V V L H L
A0 to A8 x x x V V V V V x x x V V V V V
x x x x x x x x x x x x x x x x
H H H
READ
READ A H WRIT H
WRIT A H ACTV PRE PALL REF, SELF MRS H H H H H
Row address strobe and bank ACTVM H active and Masked write enable Column address and block write BWRIT command H
Block write with auto precharge BWRITA H Special mode register set SMRS H
Notes: 1. H: VIH. L: V IL. x: VIH or VIL. V: Valid address input. 2. When CS is high, the HM5216326 ignores command input. Internal operation is held. 3. Illegal if the burst length is 1, 2, 4 or 8.
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HM5216326 Series
DQM Truth Table
CKE n-1 H H
Function Ith byte write enable/output enable Ith byte write input/output disable
Symbol ENB i MASK i
n x x
DQM i L H
Note: H: VIH. L: V IL. x: VIH or VIL. i = 0, 1, 2, 3. DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31
CKE Truth Table
CKE n-1 H L L CS H x x L L L H L H L H RAS x x x L L H x H x H x CAS WE x x x L L H x H x H x x x x H H H x H x H x
Current state Active Any
Function Clock suspend mode entry Clock suspend
n L L H H L L L H H H H
DSF x x x L L x x L L x x
Address x x x x x x x x x x x
Clock suspend Clock suspend mode exit Idle Idle Idle
Auto refresh command REF H Self refresh entry SELF Power down entry H H H
Self refresh
Self refresh exit
L L
Power down
Power down exit
L L
Note: H: VIH. L: V IL. x: VIH or VIL.
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HM5216326 Series
Function Truth Table
The following tables show how each command works and what command can be executed in the state given. Current state CS Precharge H L L L L L L L L L Idle H L L L L L L L L L L L Row active H L L L L L L L L L L RAS CAS WE x H H H H L L L L H x H H H H L L L L L H L x H H H H L L L L H L x H H L L H H L H L x H H L L H H L L H L L x H H L L H H L H L L x H L H L H L x H L x H L H L H L H L H L L x H L H L H L x H L L DSF Address x x L L L L L x H H x x L L L L L L L H H H x x L L L L L L H H H BA, RA ACTVM x x x Command DESL NOP BST Operation NOP -> Idle after tRP NOP -> Idle after tRP ILLEGAL*2, * 6 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*3 ILLEGAL ACTVM ILLEGAL*2
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA x x x ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A ILLEGAL*2 DESL NOP BST NOP NOP NOP*6 ILLEGAL*2 ILLEGAL*2 Bank and row active NOP*3 Auto self refresh*4 Mode register set*4 Bank and row active and write per bit enable
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x MODE BA, RA ACTV PRE, PALL REF, SELF MRS ACTVM
BA, CA, A9 BWRIT/BWRIT A ILLEGAL*2 Special MODE SMRS x x x DESL NOP BST Special mode register set*5 NOP NOP NOP*6 Start read Start write ILLEGAL*2 Precharge ILLEGAL ILLEGAL*2
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A Start block write Special MODE SMRS Special mode register set*5
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HM5216326 Series
Current state CS Read H L L L L L L L L L Read with auto precharge H RAS CAS WE x H H H H L L L L H x x H H L L H H L H L x x H L H L H L x H L x DSF Address x x L L L L L x H H x x x x Command DESL NOP BST Operation NOP -> Burst end -> Row active NOP -> Burst end -> Row active Burst stop -> Row active*6 Term burst -> Start new read Term burst -> Start write ILLEGAL*2 Term burst -> Precharge ILLEGAL ACTVM ILLEGAL*2
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A Term burst -> Start block write x DESL NOP -> Burst end -> Precharge NOP -> Burst end -> Precharge ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2
L L L L L L L L L Write/BWrite H L L L L L L L L L
H H H H L L L L H x H H H H L L L L H
H H L L H H L H L x H H L L H H L H L
H L H L H L x H L x H L H L H L x H L
x L L L L L x H H x x L L L L L x H H
x x
NOP BST
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA x x x ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A ILLEGAL*2 DESL NOP BST NOP -> Burst end -> Write recovering NOP -> Burst end -> Write recovering Burst stop -> Row active*6 Term burst -> Start read Term burst -> Start new write ILLEGAL*2 Term burst -> Precharge ILLEGAL ACTVM ILLEGAL*2
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A Term burst -> Start block write
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HM5216326 Series
Current state CS Write/Bwrite with auto precharge H RAS CAS WE x x x DSF Address x x Command DESL Operation NOP -> Burst end -> Write recovering with precharge NOP -> Burst end -> Write recovering with precharge ILLEAGL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2
L L L L L L L L L Write/Bwrite recovering H L L L L L L L L L Write/Bwrite H recovering with precharge L L L L L L L L L
H H H H L L L L H x H H H H L L L L H x
H H L L H H L H L x H H L L H H L H L x
H L H L H L x H L x H L H L H L x H L x
x L L L L L x H H x x L L L L L x H H x
x x
NOP BST
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA x x x ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A ILLEGAL*2 DESL NOP BST NOP -> Row active after t WR/tBWR NOP -> Row active after t WR/tBWR NOP -> Row active after t WR/tBWR* 6 Start read*2 Start new write*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA x ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A ILLEGAL*2 DESL NOP -> Precharge after t WR/tBWR NOP -> Precharge after t WR/tBWR ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2
H H H H L L L L H
H H L L H H L H L
H L H L H L x H L
x L L L L L x H H
x x
NOP BST
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A ILLEGAL*2
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HM5216326 Series
Current state CS Row activating H L L L L L L L L L Refresh(auto precharge) H L L L L Mode register H set L L L L Special Mode H register set L L L L RAS CAS WE x H H H H L L L L H x H H H L x H H H L x H H H L x H H L L H H L H L x H H L x x H H L x x H H L x x H L H L H L x H L x H L x x x H L x x x H L x x DSF Address x x L L L L L x H H x x L x x x x L x x x x L x x x x x Command DESL NOP BST Operation NOP -> Row active after tRCD NOP -> Row active after tRCD NOP -> Row active after t RCD* 6 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2
BA, CA, A9 READ/READ A BA, CA, A9 WRIT/WRIT A BA, RA BA, A9 x BA, RA x x x BA, CA, A9 x x x x BA, CA, A9 x x x x BA, CA, A9 x DESL NOP BST DESL NOP BST ACTV PRE, PALL
BA, CA, A9 BWRIT/BWRIT A ILLEGAL*2 DESL NOP BST NOP -> Idle after tRC NOP -> Idle after tRC NOP -> Idle after tRC* 6 ILLEGAL ILLEGAL NOP -> Idle after tRSC NOP -> Idle after tRSC ILLEGAL ILLEGAL ILLEGAL NOP -> Idle after tRSC or row active after tSBW NOP -> Idle after tRSC or row active after tSBW ILLEGAL ILLEGAL ILLEGAL
Notes: 1. H: VIH. L: V IL. x: VIH or VIL. 2. To execute this command for the current bank is illegal. However this command can be executed for another bank depends on the state of another bank. 3. NOP for the current bank or the bank in idle state. Precharge for the bank in other state. 4. Illegal, if both banks are not in idle state. 5. Illegal, if another bank is not in active or idle state. 6. In burst read/write, if BL is set to 1, 2, 4, 8, to try to execute BST command is illegal.
31
HM5216326 Series
Operations of HM5216326 Series
Power on sequence: In order to get rid of data contention of I/O bus when power on, the following power on sequence recommended to be performed before any operation. 1. 2. 3. 4. Apply power and start clock. Keep a NOP condition. Maintain stable power, stable clock, and NOP condition for 200 s. Execute precharge command (PALL: A9 = HIGH). Execute 8 or more auto refresh commands (REF) tRP after the precharge command as dummy. An interval tRC is necessary between two consecutive auto refresh commands. 5. Execute a mode register set command (MRS) tRC after the last auto refresh command input.
Power on Sequence
CLK tRP Command Address NOP
PALL
A9='H'
REF
REF
MRS
OP CODE
ACTV
t RC
t RC
t RSA
Repeat this auto-refresh cycle 8 times or more
Read/Write Operations Bank active: A read/write operation begins with a bank active command (ACTV or ACTVM). The bank active command determines a bank (A10) and a row address (AX0 to AX9). For the bank and the row, a read/write command can be applied. An interval not less than tRCD, after an ACTV/ ACTVM command to a read/write command, is required. Read operation: Burst length (BL), CAS latency (CL) and burst type (BT) of the mode register are referred when read command is executed. Burst length (BL) determines the length of a sequential data by a single read command, which can be set to 1, 2, 4, 8 or 256 (full-page). Starting address of a burst data is defined by column address (AY0 to AY7) and bank select address (A10) loaded through A0 to A9 in the cycle when the read command is issued. CAS latency (CL) determines the delay of data output after read command input. When burst length is 1, 2, 4 or 8, DQ buffers automatically become High-Z at the next cycle after completion of burst read. When burst length is full-page (256), data are repeatedly output until a burst stop command, a read/write command or a precharge command is input.
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HM5216326 Series
Burst Length
CLK t RCD Command Address ACT row BL=1 BL=2 DQout BL=4 BL=8 BL=Full page read
column
0 0 0 0 0 1 1 1 1 2 2 2 3 3 3 4 4 5 5 6 6 7 7 256 0 1
BL: Burst Length CAS Latency = 2 BT: sequential
CAS Latency
CLK t RCD Command Address ACT row CL= 1 CL= 2 CL= 3 read
column
0
1 0
2 1 0
3 2 1 3 2 3 Burst Length = 4 CL = CAS Latency BT: sequential
DQ out
Burst operation (on read or write): One burst data output/input by one read/write command are included in a column block determined by A1 to A7 in case BL (Burst Length) = 2, by A2 to A7 in case BL = 4 and by A3 to A7 in case BL = 8. Burst type (BT) determines the order how data of the column block are output/input. There are two burst types, sequential (wrap around) or interleave. The order of the burst data depends also on the start cloumn location of the burst data. See tables below for details.
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HM5216326 Series
Column Block BL = 2
Column location A0 0 1 A1 a1 a1 Column block location A2 a2 a2 A3 a3 a3 A4 a4 a4 A5 a5 a5 A6 a6 a6 A7 a7 a7
Note: a1, a2, a3, a4, a5, a6, a7; VIH or VIL.
BL = 4
Column location A0 0 1 0 1 A1 0 0 1 1 Column block location A2 a2 a2 a2 a2 A3 a3 a3 a3 a3 A4 a4 a4 a4 a4 A5 a5 a5 a5 a5 A6 a6 a6 a6 a6 A7 a7 a7 a7 a7
Note: a2, a3, a4, a5, a6, a7; VIH or VIL.
BL = 8
Column location A0 0 1 0 1 0 1 0 1 A1 0 0 1 1 0 0 1 1 A2 0 0 0 0 1 1 1 1 Column block location A3 a3 a3 a3 a3 a3 a3 a3 a3 A4 a4 a4 a4 a4 a4 a4 a4 a4 A5 a5 a5 a5 a5 a5 a5 a5 a5 A6 a6 a6 a6 a6 a6 a6 a6 a6 A7 a7 a7 a7 a7 a7 a7 a7 a7
Note: a3, a4, a5, a6, a7; VIH or VIL.
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HM5216326 Series
The Order of Burst Operation BL = 2
Start column location A0 0 1 Order in decimal BL = 2 Sequential 0 1 1 0 Interleave 0 1 1 0
BL = 4
Start column location A0 0 1 0 1 A1 0 0 1 1 Order in decimal BL = 4 Sequential 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 Interleave 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0
BL = 8
Start column location A0 0 1 0 1 0 1 0 1 A1 0 0 1 1 0 0 1 1 A2 0 0 0 0 1 1 1 1 Order in decimal BL = 8 Sequential 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 Interleave 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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HM5216326 Series
Write operation: OPCODE (A10, A9, A8) of the mode register is referred when a write command is executed as well as BL (Burst Length) and BT (Burst Type). CL (CAS Latency) is ignored and CL is fixed to 0 for write operation, that is, write data input starts on the same cycle when the write command is issued. Burst write: Before executing a burst write operation, OPCODE (A10, A9, A8) should be set to (0, 0, 0). Burst length (BL) determines the length of a sequential data by the burst write command, which can be set to 1, 2, 4, 8 or 256 (full-page). Starting address of a burst data is defined by column address (AY0 to AY7) and bank select address (A10) loaded through A0 to A10 in the cycle when the burst write command is issued.
CLK t RCD Command Address ACT row BL=1 BL=2 DQ in BL=4 BL=8 BL=Full page write
column
0 0 0 0 0 1 1 1 1 2 2 2 3 3 3 4 4 5 5 6 6 7 7 256 0 1
BL:Burst Length CAS Latency = 1, 2, 3
Single write: Before executing a single write operation, OPCODE (A10, A9, A8) should be set to (0, 1, 0). In the single write operation, data are only written to the single column defined by the column address and the bank select address loaded at the write command set cycle regardless of the defined burst length. (The latency of data input is 0).
CLK t RCD Command Address DQ in ACT row write
column
0 BL: Burst Length = 1, 2, 4, 8, full page
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HM5216326 Series
Write per bit: To use write per bit function, 1. Set mask data in advance, which define DQ paths to be masked, to the MASK register by SMRS command. An interval not less than tRSC after a SMRS command to an ACTVM command is necessary. 2. Use ACTVM command to activate the bank for which write per bit operation is performed. An interval not less than tRCD, after an ACTVM command to a write or a block write command, is necessary. 3. Execute a write or a block write command. In this write operation, DQ paths defined by mask register are masked to preserve the previous data. (See the example below) Special Mode Register Set (Load Mask) in Idle State and Write Per Bit
CLK t RCD Command Address DQ in
SMRS
A5=1 A6=0
ACTM
write
column
row
mask data
0 tRSC
1 BL: Burst Length = 2
Special Mode Register Set (Load Mask) in Active State and Write Per Bit
CLK
Command Address DQ in
SMRS
A5=1 A6=0
write col 0 tSBW 1 BL: Burst Length = 2
mask data
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HM5216326 Series
Write Per Bit Example

DQ input data A B MASK data stored in the MASK register 0 1 1 0 1 Data to be written DQ 0 DQ 1 DQ 2 DQ 3 B C D E C DQ 28 E DQ 29 DQ 30 DQ 31 F G H 0 1 0 data through this bit will not be written. G
Block write: Before executing a block write command, a color data (32 bit) should be set in advance, which is allowed to be written in 8 columns at one write cycle, to the color register by SMRS command. An interval not less than tRSC after a SMRS command to an ACTVM command is necessary. If a SMRS command is executed in active state to set the color register, an interval not less than tSBW is required before executing a block write command after the SMRS command. If a block write command is applied to the bank which is activated by ACTVM command, write per bit function is also available. DQ inputs at the cycle, when a block write command is executed, are reffered to mask the specific columns. See the example below. Special Mode Register Set (Load Mask) in Idle State and Block Write
CLK t RCD Command Address DQ in
SMRS
A5=0 A6=1 Color data
ACTM
Bwrite
column
Column MASK
row
t RSC
BL: Burst Length = 2
38

. ' $ & ,
Block Write Example with Write Per Bit Color data A B MASK data 0 1 0 Data to be written (Column block) A B 0 1 7 A B A B D E D D D 24 30 31 1 1 0 E E E G G H 0 G H 1 G H 7 H DQ input 1 0
lu Co mn s ma k
HM5216326 Series
DQ 0 DQ 1 DQ 7
Column location
1
data through this bit will not be written.
DQ 24 DQ 25 DQ 31
1 1 0
Co
lu
m mn
as
k
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HM5216326 Series
Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, so no precharge commands are necessary after each read operation. The command next to this command must be a bank active (ACTV, ACTVM) command. In addition, an interval defined by l APR is required prior to the next command. Note: In executing read with auto precharge command, every command to another bank is ignored until internal precharge completed.
CAS latency 3 2 1 2 1 0 Precharge start cycle cycle before the last data out cycle before the last data out cycle before the last data out
CLK t RCD Command CL=1 DQ out Command CL=2 DQ out ACT read ACT read ACT IAPR 0 1 2 3 ACT IAPR 0 1 2 3
Command CL=3 DQ out
ACT
read
ACT IAPR 0 1 2 3
Internal precharge starts here
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HM5216326 Series
Write with auto precharge: In this operation, since precharge is automatically performed after completion of a burst write or a single write operation, so no precharge commands are necessary after the write operation. The command next to this command must be a bank active command (ACTV, ACTVM). In addition, an interval of lAPW is required between the last valid data and the following command. Note: In executing write with auto precharge command, every command to another bank is ignored until internal precharge completed. Burst Write (Burst Length = 4)
CLK
Command Address
ACT row
write
column
ACT row
DQ in
0
1
2
3 IAPW
Single Write
CLK
Command Address DQ in
ACT row
write
column
ACT row
0 I APW
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HM5216326 Series
Block write with auto-precharge: In this operation, since precharge is automatically performed after completion of a block write operation, so no need to execute precharge command. The following command must be a bank active command (ACTV, ACTVM). In addition, an interval of lAPBW is required between the last valid data input and the following command. Block Write with Auto Precharge
CLK
Command Address
ACT row
Bwrite
column
ACT row IAPBW
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HM5216326 Series
Full Page Burst Stop Burst stop command during burst read: Burst stop command is used to stop data output during a fullpage burst read. This command sets the output buffer to High-Z and stops the full-page burst read. The timing, from command input to the last data, depends on CAS latency. BST command is legitimate only in case full page burst mode, and is illegal in case burst length 1, 2, 4 or 8.
CAS latency 1 2 3 BST to valid data 0 1 2 BST to high impedance 1 2 3
CAS Latency = 1, Burst Length = Full Page
CLK Command DQ out IBSH = 1 IBSR = 0 BST
CAS Latency = 2, Burst Length = Full Page
CLK Command DQ out IBSH = 2 IBSR = 1 BST
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HM5216326 Series
CAS Latency = 3, Burst Length = Full Page
CLK Command DQ out IBSH = 3 IBSR = 2 BST
Burst stop command at burst write: For full page burst write cycle, when a burst stop command is issued, the write data at that cycle and the following write data input are ignored. The BST command is legitimate only in case full page burst mode, and is illegal for burst length 1, 2, 4 or 8. Burst Length = Full Page
CLK
Command
Burst stop Precharge
DQ input
in
in t WR
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HM5216326 Series
DQM Control The DQM i (i=0, 1, 2, 3) controls the ith byte of DQ data. DQM control operation for read and for write are different in terms of latency. Reading: When data are read, output buffer can be controlled by DQMi. By setting DQMi to LOW, the corresponding DQ output buffers become active. By setting DQMi to HIGH, the corresponding DQ output buffers are made floated so that the ith byte of data are not driven out. The latency of DQM operation for read operation is 2.
CLK DQM DQout 0 1 3 IDOD= 2 Latency
Writing: Input data can be controlled by DQMi. While DQMi is LOW, data is driven into the HM5216326. By setting DQMi to HIGH, corresponding ith byte of DQ input data are kept from being written to the HM5216326 and the previous data are protected. The latency of DQM control operation is 0.
CLK DQM DQin 0 1 3 I DID = 0 Latency

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HM5216326 Series
Refresh Auto Refresh: All the banks must be precharged before executing an auto-refresh command. Auto refresh command increments the internal counter every time when it is executed. This command also determines the row to be refreshed. Therefore external address specification is not necessary. Refresh cycle is 2048 cycles/32 ms. (2048 cycles are required to refresh all the row addresses.) All output buffers become HighZ after auto-refresh start. No prechrage commands are necessary after this operation. Self Refresh: When issuing a self refresh command, by changing the level on CKE pin from HIGH to LOW simultaneously, a self refresh operation starts and is kept while CKE is LOW. During the selfrefresh operation, all data schedule to be refreshed internally. This operation managed by an internal refresh timer. After exiting from the self refresh, since the last row refreshed cannot be determined, autorefresh commands should immediately be performed for all addresses. Change the level on the CKE pin from LOW to HIGH to exit from Self refresh mode. Others Power Down Mode: Power down mode is a state in which all input buffers except the CKE input buffer are made inactive and clock signal is masked to cut power dissipation. To enter into power down mode, CKE should be set to low. Power down mode is kept as long as CKE is low. Change the level on the CKE pin from LOW to HIGH to exit from Power down mode. In this mode, internal refresh is not performed. Clock Suspend: The HM5216326 enters into clock suspend mode from active mode by setting CKE to low. There are several types of clock suspend mode depends on the state when CKE level is changed from HIGH to LOW. ACTIVE clock suspend: If CKE-transition (1 to 0) happens during a bank active state, the bank active status is kept. Any input signals are ignored during this mode. READ and READ A suspend: If CKE transition (1 to 0) happens during a read operation, the read operation is kept or DQ output data is driven out until completion. Any input signals are ignored during this mode. WRITE (BLOCK WRITE) and WRITE A (BLOCK WRITE A) suspend: If CKE-transition (1 to 0) happens during a write operation, though any input signals include DQ input data ignored, the write operation is kept until completion. Any input signals are ignored during this mode. Change the level on the CKE pin from LOW to HIGH to exit from Clock suspend mode.
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HM5216326 Series
Command Intervals Read Command to Read Command Interval: 1. Operation for a column in the same row: Read command can be issued every cycle. Note that the latest read command has the priority to the preceding read command, that is, any read command can interrupt the preceding burst read operation to get valid data aimed by this interruption.
CLK tRCD Command Address A10(BS) DQ out A0 B0 B1 B2 B3 CAS Latency = 3 Burst Length = 4 Bank 0 ACT row read read A B
Bank 0 Active
Column A
Column B Column A Column B
read
read
Dout
Dout
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank-active command before executing the new read command. 3. Operation for another bank: For another bank in active state, the new read command can be executed in the next cycle after the preceding read command is issued. If another bank is in idle state, a bank active command should be executed before executing the new read command.
CLK tRRD Command Address A10(BS) DQ out A0 B0 B1 B2 B3 CAS Latency = 3 Burst Length = 4 Bank 0 Bank1 Column A Column B Bank0 Bank1 Active Active read read Dout Dout ACT 0 ACT 1 read read A B
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HM5216326 Series
Write Command to Write Command Interval: 1. Operation for a column in the same row : Write command can be issued every cycle. Note that the latest write command has the priority to the preceding write command, that is, any write command can interrupt the preceding burst write operation to get valid data
CLK tRCD Command Address ACT row write write A B
A10(BS) DQ in A0 B0 B1 B2 B3 Burst Write Mode CAS Latency = 3 Burst Length = 4
Bank 0 Active
Column A Column B
write
write
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before executing the following write command. 3. Operation for another bank: For another bank in active state, the following burst write command can be executed in the next cycle after the preceding write command is issued. If another bank is in the idle state, bank active command should be executed.
CLK tRRD Command Address A10(BS) ACT 0 ACT 1 write write A B
DQ in
A0
B0
B1
B2
B3
Bank 0 Bank1 Bank0 Bank 1 Active Active write write
Burst Write Mode CAS Latency = 3 Burst Length = 4
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HM5216326 Series
Block Write Command to Write or Block Write Command Interval: 1. Operation for a column in the same row: It is necessary to take no less than tBWC internal between a block write and another block write or the following write. If tCK is less than tBWC , NOP command should be issued for the cycle between a block write command and the following write or another block write command.
CLK t RCD Command Address ACT row Bank 0 Active t BWC
Bwrite
Bwrite /Write
A
B
Column A Column B Block write Block write /Write
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before the following write or another block write operation. 3. Operation for another bank: To execute the following write command or another block write command for another bank in active state, tBWC interval to the next command is necessary. If another bank is in the idle state, bank active command should be executed. If t CK is less than tBWC , NOP command should be issued for the cycle between block write command and the following write or another block write command.
CLK t RRD Command Address A10(BS) Bank 0 Active Bank1 Column A Column B Active Block write Block write /Write ACT 0 ACT 1 t BWC
Bwrite
Bwrite /Write
A
B
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HM5216326 Series
Read Command to Write or Block Write Command Interval: 1. Operation for a column in the same row: The write or the block write command following the preceding read command can be performed after an interval of no less than 1 cycle. To set DQ output High-Z when data are driven in, DQM must be used depending on CAS latency as the timing shown below. Note that the latest write or block write command has the priority to the preceding read command, that is, any write or block write command can interrupt the preceding burst read operation to get valid data.
CLK Command CL= 1 DQM CL= 2 CL= 3 DQ in DQ out 0 1 2 3 read write
High-Z
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before executing the next write or another block write command. 3. Operation for another bank: For another bank in active state, the following write or block write command can be executed from the next cycle after the preceding write command is issued. If another bank is in idle state, bank active command should be executed, prior to execute the following write or block write command.
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HM5216326 Series
Write Command to Read Command Interval: 1. Operation for a column in the same row: The read command following the preceding write command can be performed after an interval of no less than 1cycle. Note that the latest read command has the priority to the preceding writing command, that is, any read command can interrupt the preceding write operation to get valid data. WRITE to READ Command Interval (1)
CLK Command DQM DQ in DQ out
Column A
write read
A0 B0 write read B1 B2 B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank 0
CAS Latency Dout
Column B Column B
WRITE to READ Command Interval (2)
CLK Command DQM DQ in DQ out
Column A
write
read
A0
A0 B0 B1 B2 B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank 0
write read
CAS Latency Dout
Column B Column B
2. Operation for a column in other row of the same bank: To execute the following read command, it is necessary to execute a precharge command and a bank active command. 3. Operation for another bank: For another bank in active state, the following read command can be executed from the next cycle after the preceding write command is issued. If another bank is in idle state, a bank active command should be executed prior to execute the following read command.
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HM5216326 Series
Block Write Command to Read Command Interval: 1. Operation for a column in the same row : Within the same row, it is necessary to take no less than t BWC between a block write and the following read command. If tCK is less than tBWC, NOP command should be issued for the cycle between a block write command and the following read command. Block Write Command to Read Command Interval
CLK Command DQM
Bwrite
read
t BWC
DQ out
Column A
B0 Block write read
B1
B2
B3 CAS Latency = 1 Burst Length = 4
CAS Latency Dout
Column B Column B
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before the following write or another block write operation. 3. Operation for another bank: To execute a read command for another bank in active state, tBWC interval to the next command is necessary. If another bank is in idle state, bank active command should be executed. If t CK is less than tBWC, NOP command should be issued for the cycle between a block write command and the following read command.
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HM5216326 Series
Read Command to Precharge Command: The minimum interval between read command and precharge command is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by l EP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (Same Bank): Output All Data CAS Latency = 1, Burst Length = 4
CLK Command DQout read 0 CL = 1 1 2 Pre. 3 I EP = 0 cycle
CAS Latency = 2, Burst Length = 4
CLK Command DQout CL = 2 read 0 1 Pre. 2 3
I EP = -1cycle
CAS Latency = 3, Burst Length = 4
CLK Command DQout CL = 3 read 0 Pre. 1 2 3
I EP = -2cycle
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HM5216326 Series
READ to PRECHARGE Command Interval (Same Bank): Stop Output Data CAS Latency = 1, Burst Length = 4
CLK Command DQout read Pre. High-Z 0 I HZP = 1
CAS Latency = 2, Burst Length = 4
CLK Command DQout read Pre. High-Z 0 I HZP = 2
CAS Latency = 3, Burst Length = 4
CLK Command DQout IHZP = 3 read Pre. High-Z 0
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HM5216326 Series
Write Command to Precharge Command: The minimum interval between a write command and the following precharge command is 1 cycle. However, if the burst write operation is not finished, input must be masked by means of DQM for the cycle defined by tWR, for assurance. WRITE to Precharge Command Interval (Same Bank) Burst Length = 4 (To Stop Write Operation)
CLK Command DQM DQin A0 A1 t WR write Pre.
Burst Length = 4 (To Write All Data)
CLK Command DQM DQin A0 A1 A2 A3 tWR write Pre.
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HM5216326 Series
Block Write Command to Precharge Command Interval: The minimum interval between block write command and the following precharge command is tBWR . Block Write to Precharge Command Interval (Same Bank)
CLK Command
Bwrite
Pre. t BWR
Register set to register set interval: The minimum interval between two successive register set commands (mode/special mode) is lRR. Mode register set to spacial mode register interval
CLK
Command Address DQ in
MRS
A0-A9
SMRS A5,A6 color /mask
IRR
Special Mode Register Set to Block Write/Write Interval: The minimum interval between a special mode register set and a block write/write is tSBW. Special Mode Register Set to Burst Write Interval
CLK Command Address DQ in
SMRS A5,A6 color /mask write
column
0 tSBW
1 Burst length = 2
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HM5216326 Series
Bank Active Command Interval: 1. Operation for the same bank: The interval between two bank-active commands must be no less than tRC. 2. Operation for another bank: The interval between two bank-active commands must be no less than tRRD. Bank Active to Bank Active for the Same Bank
CLK Command Address A10(BS) t RAS t RC t RP ACT row Pre ACT row
Bank Active to Bank Active for Another Bank
CLK Command Address A10(BS) t RRD ACT row ACT row
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HM5216326 Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: Symbol VT VDD Iout PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note 1
1. VIH (max) = 5.75 V for pulse width 5 ns
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VDD, VDDQ VSS , VSS Q Input high voltage Input low voltage VIH VIL Min 3.0 0 2.0 -0.3 Max 3.6 0 4.6 0.8 Unit V V V V 1, 2 1, 3 Notes 1
Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns
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HM5216326 Series
DC Characteristics (Ta = 0 to 70C, VDD, VDDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V)
HM5216326 -8 Parameter Operating current Symbol Min I CC1 -- -10 Max Min TBD -- -12 Max Min TBD -- Max Unit Test conditions TBD mA Burst length = 1 t RC = min, CL = 3 t CK = min CKE = VIL, t CK = min CKE = VIL CLK = V o VIH Fxed i IL r CKE = VIH, NOP command t CK = min CKE = VIL, t CK = min, 1 DQ = High-Z CKE=VIH, NOP command t CK = min, DQ = High-Z t CK = min, BL = 4 2 bank operation 1 Note 1
Standby current (Bank Disable)
I CC2
-- -- --
TBD -- TBD -- TBD --
TBD -- TBD -- TBD --
TBD mA TBD mA TBD mA
Active standby current I CC3 (Bank active)
-- --
TBD -- TBD --
TBD -- TBD --
TBD mA TBD mA
Burs t operating c urrent (CL = 1) (CL = 2) (CL = 3) Refresh current Self refresh current Block write operating current Input leakage current Output leakage current Output high voltage Output low voltage Note: I CC4 I CC4 I CC4 I CC5 I CC6 I CC7 -- -- -- -- -- -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA t RC = min, CL = 3 t CK = min VIH V DD - 0.2 VIL 0.2 V t CK = min, CL = 3 1 bank operation, t RC = 150 ns 0 Vin V DD 0 Vout V DD DQ = disable I OH = -2 mA I OL = 2 mA
I LI I LO VOH VOL
-10 -10 2.4 --
10 10 -- 0.4
-10 -10 2.4 --
10 10 -- 0.4
-10 -10 2.4 --
10 10 -- 0.4
A A V V
1. I CC depends on output load condition when the device is selected. ICC (max) is specified on condition that all output pins are floated.
59
HM5216326 Series
Capacitance (Ta = 25C, VDD, VDDQ = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (Signals) Output capacitance (DQ) Symbol CI1 CI2 CO Typ -- -- -- Max 5 5 7 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM = VIH to disable Dout.
60
HM5216326 Series
AC Characteristics (Ta = 0 to 70C, VDD, VDDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V)
HM5216326 -8 Parameter System clock cycle time (CL = 1) (CL = 2) (CL = 3) CLK high pulse width CLK low pulse width Access time from CLK (CL = 1) (CL = 2) (CL = 3) Data-out hold time CLK to data-out low impedance CLK to data-out high impedance (CL = 1) (CL = 2,3) Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time Command (CS, RAS, CAS, WE, DQM, DSF) setup time Command (CS, RAS, CAS, WE, DQM, DSF) hold time Refresh/active to refresh/active command period Active to precharge on full page mode Active to precharge command period Active command to column command Precharge to active command period Symbol Min t CK t CK t CK t CH t CL t AC t AC t AC t OH t LZ t HZ t HZ t DS t DH t AS t AH t CKS t CKH t CMS t CMH t RC t RASC t RAS t RCD t RP 24 12 8 2.5 2.5 -- -- -- 2 0 -- -- 2 1 2 1 2 1 2 1 72 -- 48 24 24 Max -- -- -- -- -- 22 10 6.5 -- -- 11 6 -- -- -- -- -- -- -- -- -- -10 Min 30 15 10 3 3 -- -- -- 3 0 -- -- 3 1 3 1 3 1 3 1 90 Max -- -- -- -- -- 28 11 7.5 -- -- 13 7 -- -- -- -- -- -- -- -- -- -12 Min 36 18 12 4 4 -- -- -- 3 0 -- -- 3.5 1.5 3.5 1.5 3.5 1.5 3.5 1.5 108 Max -- -- -- -- -- 32 12 10 -- -- 15 9 -- -- -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1, 4 1, 4 1 1 1 1 1 1 1 1 1 1, 3 1 1 1, 2 1
120000 -- 120000 60 -- -- 30 30
120000 -- 120000 72 -- -- 36 36
120000 ns 120000 ns -- -- ns ns
61
HM5216326 Series
AC Characteristics (Ta = 0 to 70C, VDD, V DDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) (cont)
HM5216326 -8 Parameter The last data-in to precharge lead time (CL = 1) (CL = 2) (CL = 3) Block write to precharge lead time (CL = 1) (CL = 2) (CL = 3) Active (a) to active (b) command period Register set to active command Block write cycle time Symbol Min t WR t WR t WR t BWR t BWR t BWR t RRD t RSC t BWC 12 12 16 24 24 24 16 16 16 16 1 -- Max -- -- -- -- -- -- -- -- -- -- 5 32 -10 Min 15 15 20 30 30 30 20 20 20 20 1 -- Max -- -- -- -- -- -- -- -- -- -- 5 32 -12 Min 18 18 24 36 36 36 24 24 24 24 1 -- Max -- -- -- -- -- -- -- -- -- -- 5 32 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ms 1 1 1 1 1 1
Special mode register set to column t SBW command Transition time (rise to fall) Refresh period tT t REF
Notes: 1. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.4 V. Test load (A) is used with CL = 30 pF in general except fpr the measurement of access time (note2) and tHZ (note3). 2. Access time is measured at 1.4 V. Test load (B) is used with current source. 3. t HZ (max) defines the time at which the outputs achieves 200 mV. Test load (A) is used with CL = 5 pF and with current source. 4. When Active Suspend Exit, Power Down Exit or Self Refresh Exit is executed. CKE should be kept "H" more than 1 cycle from these Exit cycles.
62
HM5216326 Series
Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures
2.8 V
input
V SS
80% 20%
t
T
tT LVTTL interface
Output +1.4 V DQ CL 500 DQ I +1.4 V 50 30 pF
* IOL (max) = 20mA IOH (min) = -20mA Test Load (A) Test Load (B)*
63
HM5216326 Series
Relationship Between Frequency and Minimum Latency
HM5216326 Parameter CL tCK (ns) Last data in to active command (Auto precharge, same bank) Block write to active command (Auto precharge, same bank) Precharge command to high impedance Last data out to active command (Auto precharge, same bank) Last data out to precharge Column command to column command Symbol lAPW lAPBW lHZP lAPR lEP lCCD -8 3 10 5 6 3 1 -2 1 0 0 2 1 2 3 0 0 0 2 2 15 3 4 2 1 -1 1 0 0 2 1 1 2 0 0 0 2 1 -10 3 2 1 -12 3 2 1 45 2 2 1 1 0 1 0 0 2 1 0 1 0 0 0 1 Notes
30 12 18 36 15.0 22.5 2 2 1 1 0 1 0 0 2 1 0 1 0 0 0 1 5 6 3 1 3 4 2 1 2 2 1 1 5 6 3 1 -2 1 0 0 2 1 2 3 0 0 0 2 3 4 2 1 -1 1 0 0 2 1 1 2 0 0 0 2
-2 -1 0 1 0 0 2 1 2 3 0 0 0 2 1 0 0 2 1 1 2 0 0 0 2 1 0 0 2 1 0 1 0 0 0 1
Write command to data in latency lWCD DQM to data in DQM to data out CKE to CLK disable Burst stop to output valid data hold Burst stop to output high impedance Burst stop to write data ignore MRS to data in latency SMRS to data in latency Register set to register set lDID lDOD lCLE lBSR lBSH lBSW lMSD lSSD lRR
64
HM5216326 Series
Timing Waveforms
Read Cycle
t CK t CH t CL
CLK
VIH

t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH
, , , , ,, , , , ,,, , , , , , ,,
CKE
t RCD t RAS t
RP
t RC
t CMS t CMH
t CMS t CMH
t CMS t CMH
t CMS t CMH
CS
RAS
t CMS t CMH
t CMS t CMH
t CMS t CMH
t CMS t CMH
CAS
t CMS t CMH
t CMS t CMH
t CMS t CMH
t CMS t CMH
WE
t AS t AH t AS t AH
t AS t AH
t AS t AH
t AS t AH t AS t AH
A10
t AS t AH t AS t AH
t AS t AH
A9
t AS t AH
t AS t AH
A0 to A7
t CMS
t CMH
DQM
DQ(input)
tCAC
t AC
t AC
t AC
DQ(output)
t AC
Bank 0 Active
Bank 0 Read
t LZ
t OH
t OH
t OH
t HZ
Bank 0 Precharge
Burst length = 4 Bank0 Access
65
HM5216326 Series
Write Cycle
, ,
,

,
t CK t CH t CL
CLK
t RC
VIH
CKE
t RCD
t RAS
t RP
t CMS t CMH
t CMS t CMH
t CMS t CMH
t CMS t CMH
CS
, , ,
RAS
t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH
t CMS t CMH
t CMS t CMH
t CMS t CMH
t CMS t CMH
CAS
t CMS t CMH
t CMS t CMH
t CMS t CMH
t CMS t CMH
WE
t AS t AH t AS t AH
t AS t AH
t AS t AH
t AS t AH t AS t AH
A10
t AS t AH t AS t AH
t AS t AH
A9
t AS t AH
t AS t AH
A0 to A7
t CMS
t CMH
DQM
t DS t DH tDS
t DH t DS t DH t DS
t DH
DQ(input)
t WR
DQ(output)
Bank 0 Active
Bank 0 Write
Bank 0 Precharge
Burst length = 4 Bank 0 Access
66
, " " , !
! ,
", "
HM5216326 Series
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
, , , , , , ,, , , , , , ,,, , , ,
CLK CKE
VIH
CS
RAS CAS WE
A10(BS)
A0 to A7 DQM
valid
code
DQ(output) DQ(input)
t RP
t RSC
Precharge If needed
Mode register Set
Read Cycle/Write Cycle
0 1 2
3
4
5
6
CLK
CKE
VIH
CS
RAS CAS WE
A10(BS)
A0 to A7
R:a
C:a
R:b
DQM DQ (output) DQ (input) CKE
a
a+1 a+2 a+3
Bank 0 Active
Bank 0 Read
Bank 1 Active
VIH
CS
RAS CAS WE
A10(BS)
A0 to A7 DQM
R:a
C:a
R:b
DQ (output) DQ (input)
a
a+1 a+2 a+3
Bank 1 Active
Bank 0 Active
Bank 0 Write
,, , ,
R: b C: b C: b' b b+3 b' b'+1 b'+2 b'+3 High-Z t RCD
Output mask Bank 1 Active Bank 1 Read
tRCD = 3 CAS latency = 3 Burst length = 4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4
C:b
C:b'
C:b"
b
b+1 b+2 b+3 b'
Bank 1 Read
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 1 Bank 0 Read Precharge
Bank 1 Read
Bank 1 Precharge
Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4
C:b
C:b'
C:b"
High-Z
b
b+1 b+2 b+3 b'
Bank 0 Precharge
b'+1 b"
b"+1 b"+2 b"+3
Bank 1 Write
Bank 1 Write
Bank 1 Write
Bank 1 Precharge
67
, ? 7 9 8 : 2 , = 61 . '0 $ + "
3 * ? ; * " 3 , + $ 5 2 : 8 1 9 = 6 ; 4 ,
HM5216326 Series
Read/Single Write Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE
VIH
,
CS RAS CAS WE A10(BS) A0 to A7 R:a C:a R:b C:a' C:a a DQM DQ (input) DQ (output) CKE a a+1 a+2 a+3 a a+1 a+2 a+3
Bank 0 Precharge Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Bank 0 Write Read Bank 1 Precharge
VIH
CS
RAS CAS WE
A10(BS) DQM DQ (input) DQ (output)
A0 to A7
R:a
C:a
R:b
C:a
C:b C:c b c
a
a
a+1
a+3
Bank 0 Active
Bank 0 Read
Bank 1 Active
Bank 0 Write
Bank 0 Bank 0 Write Write
Bank 0 Precharge
Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst length = 4
68
HM5216326 Series
Read/Burst Write Cycle
0 1
= 5 , 1 8 0 " ! 0 ; 3 ! 1 * " 9 8 = 5 4 ,
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE A10(BS) A0 to A7 R:a C:a R:b C:a' a DQM DQ (input) DQ (output) CKE a+1 a+2 a+3 a a+1 a+2 a+3
Clock suspend Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Write Bank 0 Precharge Bank 1 Precharge
, ,
VIH
CS
RAS CAS WE
A10(BS) DQM DQ (input) DQ (output)
A0 to A7
R:a
C:a
R:b
C:a
a
a+1 a+2 a+3
a
a+1
a+3
Bank 0 Active
Bank 0 Read
Bank 1 Active
Bank 0 Write
Bank 0 Precharge
Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst length = 4
69
HM5216326 Series
Full Page Read/Write Cycle
0 1 2 3
" ,

! !", ,, "
,
4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CLK CKE
VIH
CS
RAS CAS WE
Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page
A10(BS) DQM DQ (output) DQ (input) CKE
A0 to A7
R:a
C:a
R:b
a
a+1
a+2
a+3
a-2
a-1
a
a+1
a+2
a+3
a+4
a+5
High-Z
Bank 0 Active
Bank 0 Read
Bank 1 Active
Burst stop
Bank 1 Precharge
VIH
CS
RAS CAS WE
Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page
A10(BS)
A0 to A7
R:a
C:a
R:b
DQM DQ (output) DQ (input)
High-Z
a
a+1
a+2
a+3
a+4
a+5
a+6
a+1
a+2
a+3
a+4
a+5
Bank 0 Active
Bank 0 Write
Bank 1 Active
Burst stop
Bank 1 Precharge
Auto Refresh Cycle
0
, , ,, , , , ,, , ,, ,, , , ,, ,
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLK
CKE CS
VIH
RAS
CAS WE
A10(BS)
A0 to A7 DQM
A9=1
R:a
C:a
DQ(input)
DQ(output)
High-Z
a
a+1
t RP
t RC
tRC
Precharge If needed
Auto Refresh
Auto Refresh
Active Bank 0
Read Bank 0
Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4
70
,, , ,,,, ,, ,, ,, , , , ,,,, ,, ,, , ,
CKE
CKE Low
, ! " , "

HM5216326 Series
Self Refresh Cycle
CLK CS RAS CAS WE A10(BS) A0 to A7 DQM
A9=1
DQ(input)
DQ(output)
tRP
Precharge command If needed
Self refresh entry command
Clock Suspend Mode
t CKS
0
1
2
3
4
5
6
7
CLK
High-Z
Self refresh exit ignore command or No operation
tRC
Auto refresh
Self refresh cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4
t CKH
t CKS
8
9
10
11
12
13
14
15
16
17
18
19
20
CKE
CS
RAS CAS WE
Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4
A10(BS)
A0 to A7
R:a
C:a
R:b
C:b
DQM DQ (output) DQ (input) CKE
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
Bank0 Active clock Active suspend start
Active clock Bank0 suspend end Read
Bank1 Active
Read suspend start
Read suspend end
Bank1 Read
Bank0 Precharge
Earliest Bank1 Precharge
CS
RAS CAS WE
Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4
A10(BS)
A0 to A7 DQM
R:a
C:a R:b
C:b
DQ (output) DQ (input)
High-Z
a
a+1 a+2
a+3 b
b+1 b+2 b+3
Bank0 Active
Active clock suspend start
Active clock Bank0 Bank1 supend end Write Active
Write suspend start
Write suspend end
Bank1 Bank0 Write Precharge
Earliest Bank1 Precharge
71
5* 6: .9 '2, ?8 =1 7
+ ! " 0 2 ; : 3
HM5216326 Series
Power Down Mode
t CKS
, , , , , , ,, ,, , , ,, , ,
CKE CS
CKE Low
CLK
RAS CAS WE
A10(BS)
A0 to A7 DQM
A9=1
DQ(input)
DQ(output)
tRP
Precharge command If needed
Power down entry

R: a High-Z
Power down mode exit Active Bank 0
Power down cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4
72
7 ?" 6 = 59 41 . - &8 '0 ,
* 2 ! + , 8 0 9 " ; : 3 2 + *
HM5216326 Series
Mask Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
,,,, , , , , , , , ,, , , , ,
CLK CKE
VIH
CS
RAS CAS WE
DSF A10 A9
Mask
No Mask
Ra
Rb
A0 to A7 DQM
A5 = 1
Ra
Rb
Ca
Cb
DQ in
Mask Data
a
a+2
a+3
b
b+1
t RP
t RSC
Precharge If needed
Mask register Set
Bank 0 ACTVM
Bank 1 Bank 0 ACTV Write per bit
Bank 1 Write
73
= ?+ 5 4 - , &" 1 . 70 69 '8, ,
* 2 ! 8 : 9 ; 3 " 1 2 + *
HM5216326 Series
Color Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
, , , , , ,, , , , , , , ,
CLK CKE
VIH
CS
RAS CAS WE
DSF A10 A9
Mask
No Mask
Ra
Rb
A0 to A7
A6 = 1
Ra
Rb
Ca
Cb
Cc
DQM
DQ in
Color Data
Column MASK
Column MASK
Column MASK
t RP
t RSC
Precharge If needed
Color register Set
Bank 0 ACTVM
Bank 1 ACTV
Bank 0 Mask Block Write
Bank 1 Block Write
74
? =" 6! 7, 5 49 .1 -0 &* ' 8, + 2
8 0 : 9 2 + * ; 3 1 "
HM5216326 Series
Write Cycle (with I/O Mask)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
, , , , , , ,, , ,, , ,
CLK CKE
VIH
CS
RAS CAS WE
DSF A10 A9
Ra
Rb
A0 to A7
Ra
Rb
Ca
Cb
DQM
DQ in
a
a+2 a+3
b
b+1
b+3
Bank 0 ACTVM
Bank 1 ACTV
Bank 0 Write per bit
Bank 1 Write
Bank 0 Precharge
75
,
72 6, " = 59 41 -* . '! &, ? + 8 0 9 1 * " ; : 3 2 + 8 0
HM5216326 Series
Block Write Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
, ,, ,, , , , , ,, ,
CLK CKE
VIH
CS
RAS CAS WE
DSF A10 A9
Ra
Rb
A0 to A7 DQM
Ra
Rb
Ca
Cb
Cc
Cd
DQ in
Column MASK
Column MASK
Column MASK
Column MASK
tBWC
Bank 0 ACTVM
Bank 1 Bank 0 ACTV Mask Block Write
Bank 0 Mask Block Write
Bank 1 Block Write
Bank 1 Block Write
Bank 0 Precharge
76
HM5216326 Series
Package Dimensions
HM5216326FP Series (FP-100H)
Unit: mm
22.00 0.10 20.00 80 81 16.00 0.10 14.00 51 50
100 1 0.32 0.08 0.30 0.06 0.575 30 0.10 M
31 1.40 0.05
0.17 0.05 0.15 0.04
1.60 Max
0.825
1.00 0 - 10
0.10 0.05
0.1
0.50 0.10
Hitachi Code JEDEC Code EIAJ Code Weight FP-100H MO-136 -- 0.95 g
77
HM5216326 Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
78
HM5216326 Series
Revision Record
Rev. Date 0.0 Contents of Modification Drawn by Approved by Nov. 20, 1996 Initial issue
79

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